A fractional N-PLL synthesizer is a PLL characterized in that a feedback frequency division number for frequency-dividing an output of a voltage-controlled oscillator (hereafter, VCO) is a fractional frequency division number. FIG. 23 illustrates an example of a typical fractional N-PLL synthesizer.
In FIG. 23, a fractional N-PLL synthesizer 1700 includes: a phase detector 1711 for detecting a phase difference between a reference signal and a feedback signal; a charge pump 1713 of the next stage; a low-pass filter (hereafter, LPF) 1714 of the further next stage; a VCO 1715 of the next stage; a fractional frequency divider 1712 for frequency-dividing an output of the VCO 1715; and a delta-sigma modulator 1720, and is referred to as a delta-sigma-type fractional N-PLL synthesizer.
The phase detector 1711 detects the phase difference between the reference signal and the feedback signal output from the fractional frequency divider 1712, and outputs the detected phase difference to the charge pump 1713. The charge pump 1713 outputs an amount of charge corresponding to the phase difference, to the LPF 1714.
The VCO 1715 changes an output frequency according to an output of the LPF 1714. The fractional frequency divider 1712 divides an output signal of the VCO 1715 by a predetermined division ratio, and outputs the divided signal to the phase detector 1711.
The delta-sigma modulator 1720 temporally switches the frequency division number in the fractional frequency divider 1712 between frequency division by N and frequency division (N+1), according to a set value of a numerator and a denominator of a feedback frequency division number.
For example, let Fref be a frequency of the reference signal, and N+NUM/DEN (where N, NUM, and DEN are each an integer) be the feedback frequency division number. An oscillation frequency FVCO of the output signal of the VCO 1715 is expressed asFVCO=Fref×(N+NUM/DEN)  (1)
Transforming Expression (1) yieldsFVCO=Fref×{(NUM/DEN)×(N+1)+(1−NUM/DEN)×N}  (2)
By switching the frequency division number between frequency division by N and frequency division by (N+1) in a time proportion according to Expression (2), the fractional frequency divider 1712 realizes a fractional frequency division number.
Moreover, the feedback frequency division number is aperiodically switched through the use of delta-sigma modulation. This produces an advantage that fractional spurious which is inherent spurious corresponding to switching periodicity is unlikely to occur.
However, in the system described above with reference to FIG. 23, the fractional spurious is noise-shaped toward higher frequencies by the delta-sigma modulator 1720, and so the noise component needs to be removed in the LPF 1714 constituting the PLL. Thus, the delta-sigma-type fractional N-PLL synthesizer has a problem that a lower cutoff frequency of the LPF is needed.
Here, the PLL has a function as a low-pass filter, but, when viewed from the LPF and the VCO which are elements of the PLL, functions as a high-pass filter (hereafter, HPF). Accordingly, low-frequency noise component generated from the elements such as the LPF and the VCO is removed by the function of the PLL as a low-pass filter. Low-frequency noise component can be removed more efficiently when the cutoff frequency of the low-pass filter as the function of the PLL is higher.
Due to the above-mentioned circumstances, the delta-sigma-type fractional N-PLL synthesizer cannot sufficiently remove low-frequency noise generated from the LPF and the VCO constituting the PLL, resulting in that a problem of degradation in output signal performance (jitter) of fractional N-PLL synthesizers still remains.
FIG. 24 is a diagram illustrating a fractional N-PLL synthesizer according to a system that uses an accumulator, as another conventional example different from that in FIG. 23.
In FIG. 24, a fractional N-PLL synthesizer 1800 includes: a phase detector 1811 for detecting a phase difference between a reference signal and a feedback signal; a charge pump 1813 of the next stage; a low-pass filter (hereafter, LPF) 1814 of the further next stage; a VCO 1815 of the next stage; a fractional frequency divider 1812 for frequency-dividing an output of the VCO 1815; and an accumulator 1820 for periodically switching the frequency division number of the fractional frequency divider 1812, and is referred to as an accumulator-type fractional N-PLL.
The accumulator-type fractional N-PLL employs a system of realizing a fractional frequency division number by periodically switching the frequency division number of the fractional frequency divider 1812 according to an output of the accumulator 1820. In this system, there is no need to remove high-frequency noise because the delta-sigma modulator as in the system in FIG. 23 is not included, and therefore the cutoff frequency of the low-pass filter can be set higher. The system is thus excellent in that low-frequency noise generated from the LPF and the VCO constituting the PLL can be sufficiently removed to achieve improved output signal performance (jitter).